This invention deals with conditional instruction execution. Conditional instruction execution is typically accomplished by determining the status of a data register and executing or not executing the instruction depending upon this status. It is known in the art to use a zero/non-zero determination for this conditional execution.
Conditional instruction execution can be advantageously employed instead of conditional branching. In deeply pipelined data processors taking a conditional branch typically results in later fetched instructions in the pipeline being no longer on the instruction path through the program. In the prior art these later fetched instructions are flushed and new instructions on the branch instruction path are fetched. This results in a delay during which the instructions on the new branch instruction path catch up to the point where instructions were flushed. This delay is called a pipeline hit. The amount this slows the data processor operation is dependent upon the pipeline depth and the frequency of taken conditional branches.
Conditional instruction execution does not involve a pipeline hit. The program instruction path is unchanged and no instructions need to be flushed. A typical program data path using conditional branches selects an alternative data processing operation based upon the condition. Then the two branches merge for additional processing. This program data path can be easily implemented using conditional instruction execution. The alternate data processing operations are made conditional on the same condition in opposite senses. Based upon the condition, one data processing operation is executed and the other is not executed. This performs the desired alternative operation. If the alternate branches are short, ideally one instruction, then the conditional execution instruction path could be shorter than the conditional branch instruction data path. For data processors that can perform more than one instruction at a time, such as a very long instruction word (VLIW) processor or a super-scalar processor, the alternate data processing operations may be scheduled during the same instruction cycle. In this case condition instruction execution typically takes the same number of instruction cycles as a conditional branch instruction path when the branch is taken. Accordingly, conditional instruction execution may be advantageous over conditional branch operations in many instances.